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CY28349OC Datasheet(PDF) 11 Page - SpectraLinear Inc |
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CY28349OC Datasheet(HTML) 11 Page - SpectraLinear Inc |
11 / 20 page CY28349 Rev 1.0, November 24, 2006 Page 11 of 20 Bit 6 -- ROCV_FREQ_M6 If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency.when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 Bit 5 -- ROCV_FREQ_M5 0 Bit 4 -- ROCV_FREQ_M4 0 Bit 3 -- ROCV_FREQ_M3 0 Bit 2 -- ROCV_FREQ_M2 0 Bit 1 -- ROCV_FREQ_M1 0 Bit 0 -- ROCV_FREQ_M0 0 Data Byte 12 (continued) Bit Pin# Name Pin Description Power On Default Data Byte 13 Bit Pin# Name Pin Description Power On Default Bit 7 -- CPU_FSEL_N7 If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 Bit 6 -- CPU_FSEL_N6 0 Bit 5 -- CPU_FSEL_N5 0 Bit 4 -- CPU_FSEL_N4 0 Bit 3 -- CPU_FSEL_N3 0 Bit 2 -- CPU_FSEL_N2 0 Bit 1 -- CPU_FSEL_N1 0 Bit 0 -- CPU_FSEL_N0 0 Data Byte 14 Bit Pin# Name Pin Description Power On Default Bit 7 -- Pro_Freq_EN Programmable output frequencies enabled 0 = Disabled 1 = Enabled 0 Bit 6 -- CPU_FSEL_M6 If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 Bit 5 -- CPU_FSEL_M5 0 Bit 4 -- CPU_FSEL_M4 0 Bit 3 -- CPU_FSEL_M3 0 Bit 2 -- CPU_FSEL_M2 0 Bit 1 -- CPU_FSEL_M1 0 Bit 0 -- CPU_FSEL_M0 0 Data Byte 15 Bit Pin# Name Pin Description Power On Default Bit 7 -- Reserved Reserved 0 Bit 6 -- Reserved Reserved 0 Bit 5 -- Reserved Reserved 0 Bit 4 -- Reserved Reserved 0 Bit 3 -- Reserved Reserved 0 Bit 2 -- Reserved Reserved 0 Bit 1 -- Vendor Test Mode Reserved. Write with “1” 1 Bit 0 -- Vendor Test Mode Reserved. Write with “1” 1 |
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