CY28342

Rev 1.0, November 20, 2006

Page 7 of 21

Byte 7: PCI Clock Register (All bits are Read and Write functional)

Bit

@Pup

Pin#

Name

Description

7

1

15

PCI_F0

PCI_F0 output control 1 = enabled, 0 = forced LOW.

6

1

14

PCI_F1

PCI_F1 output control 1 = enabled, 0 = forced LOW.

5

1

23

PCI5

PCI5 output control 1 = enabled, 0 = forced LOW.

4

1

22

PCI4

PCI4 output control 1 = enabled, 0 = forced LOW.

3

1

21

PCI3

PCI3 output control 1 = enabled, 0 = forced LOW.

2

1

20

PCI2

PCI2 output control 1 = enabled, 0 = forced LOW.

1

1

17

PCI1

PCI1 output control 1 = enabled, 0 = forced LOW.

0

1

16

PCI0

PCI0 output control 1 = enabled, 0 = forced LOW.

Byte 8: Silicon Signature Register (all bits are Read-only)

Bit

@Pup

Description

7

1

Vendor ID

1000 = Cypress

60

50

40

3

0

Revision ID

20

10

00

Byte 9: Peripheral Control Register (All bits are Read and Write)

Bit

@Pup

Pin#

Name

Description

71

33

PD#

PD# Enable. 0 = enable, 1 = disable.

60

0 = when PD# asserted LOW, CPU(0:1)T stop in a high state, CPU(0:1)C stop in

a LOW state. 1 = when PD# asserted LOW, CPU(0:1)T and CPU(0:1)C stop in H-Z.

5

1

27

48M

48M output control 1 = enabled, 0 = forced LOW.

4

1

26

48M_24M

48M_24M output control 1 = enabled, 0 = forced LOW.

3

0

26

48M_24M

48M_24M, 0 = pin 26 output is 24MHz, 1= pin 28 output is 48 MHz.

2

0

SS2 Spread Spectrum control bit (0= down spread, 1= center spread).

1

0

SS1 Spread Spectrum control bit. See Table 10.

0

0

SS0 Spread Spectrum control bit. See Table 10.

Byte 10: Peripheral Control Register (All bits are Read and Write functional)

Bit

@Pup

Pin#

Name

Description

7

1

47

SDCLK

SDCLK output enable 1 = enabled, 0 = disabled.

6

1

4

REF2

REF2 output control 1 = enabled, 0 = forced LOW.

5

1

3

REF1

REF1 output control 1 = enabled, 0 = forced LOW.

4

1

2

REF0

REF0 output control 1 = enabled, 0 = forced LOW.

3

1

10

ZCLK1

ZCLK1 output enable 1 = enabled, 0 = disabled.

2

1

9

ZCLK0

ZCLK0 output enabled 1 = enabled, 0 = disabled.

1

1

30

AGP1

AGP1 output enabled 1 = enabled, 0 = disabled.

0

1

31

AGP0

AGP0 output enabled 1 = enabled, 0 = disabled.