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CY28325OXC-3T Datasheet(PDF) 10 Page - SpectraLinear Inc |
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CY28325OXC-3T Datasheet(HTML) 10 Page - SpectraLinear Inc |
10 / 18 page CY28325-3 Rev 1.0, November 21, 2006 Page 10 of 18 2 – WD_TO_STAT US Watchdog Timer Time-out Status Bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write) 0 1 – WD_EN 0 = Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note:CY28325-3 will generate system reset, re-load a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, CY28325-2 will not respond to any attempt to change the output frequency via the SMBus control bytes. System software can unlock the CY28325-3 from its recovery frequency mode by clearing the WD_EN bit. 0 0 – Reserved Reserved 0 Data Byte 10 Bit Pin# Name Pin Description Power-on Default 7 – CPU_CS_F Skew2 CPU_CS_F Skew Control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 0 6 – CPU_CS_F Skew1 0 5 – CPU_CS_F Skew0 0 4 – CPU_Skew2 CPUT_0:1 and CPUC_0:1 Skew Control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 0 3 – CPU_Skew1 0 2 – CPU_Skew0 0 1 – AGP_Skew1 AGP Skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps 0 0 – AGP_Skew0 0 Data Byte 11 Bit Pin# Name Pin Description Power-on Default 7 – ROCV_FREQ_N7 If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 6 – ROCV_FREQ_N6 0 5 – ROCV_FREQ_N5 0 4 – ROCV_FREQ_N4 0 3 – ROCV_FREQ_N3 0 2 – ROCV_FREQ_N2 0 1 – ROCV_FREQ_N1 0 0 – ROCV_FREQ_N0 0 Data Byte 9 (continued) Bit Pin# Name Pin Description Power-on Default |
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