CY28325-3

Rev 1.0, November 21, 2006

Page 8 of 18

6

8

SEL_48MHZ

0 = 24 MHz

1 = 48 MHz

0

5

7

48MHz

1 = Enabled, 0 = Disabled

1

4

8

24_48MHz

1 = Enabled, 0 = Disabled

1

3

10

PCI_F

1 = Enabled, 0 = Disabled

1

2

27

AGP2

1 = Enabled, 0 = Disabled

1

1

26

AGP1

1 = Enabled, 0 = Disabled

1

0

23

AGP0

1 = Enabled, 0 = Disabled

1

Data Byte 4

Bit

Pin#

Name

Pin Description

Power-on

Default

7

–

PCI_Skew1

PCI skew control

00 = Normal

01 = –500 ps

10 = Reserved

11 = +500 ps

0

6

–

PCI_Skew0

0

5

–

WD_TIMER4

These bits store the time-out value of the Watchdog Timer. The scale

of the timer is determine by the prescaler. The timer can support a

value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the

prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80

sec. When the Watchdog Timer reaches “0,” it will set the

WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled.

1

4

–

WD_TIMER3

1

3

–

WD_TIMER2

1

2

–

WD_TIMER1

1

1

–

WD_TIMER0

1

0

–

WD_PRE_SCALER

0 = 150 ms

1 = 2.5 sec

0

Data Byte 5

Bit

Pin#

Name

Pin Description

Power-on

Default

7

7

48MHz_DRV

48-MHz clock output drive strength

0 = Normal

1 = High Drive

1

6

8

24_48MHz_DRV

24_48 MHz clock output drive strength

0 = Normal

1 = High Drive

1

5

45

APCI1

(Active/Inactive)

1

4

46

APIC0

(Active/Inactive)

1

3

–

SW_MULTSEL1

IREF multiplier

00 = Ioh is 4 × IREF

01 = Ioh is 5 × IREF

10 = Ioh is 6 × IREF

11 = Ioh is 7 × IREF

0

2

–

SW_MULTSEL0

0

1

1

REF

(Active/Inactive)

1

0

–

MULTSEL_Override This bit control the selection of IREF multipler.

0 = HW control; IREF multiplier is determined by MULTSEL1 input pin

1 = SW control; IREF multiplier is determined by SW_MULTSEL[0:1]

0

Data Byte 6

Bit

Pin#

Name

Pin Description

Power-on

Default

7

–

Reserved

Reserved

1

6

–

Reserved

Reserved

1

Data Byte 3

Bit

Pin#

Name

Pin Description

Power-on

Default