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ADC14L020CIVY Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # ADC14L020CIVY
Description  14-Bit, 20MSPS, 150 mW A/D Converter
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC14L020CIVY Datasheet(HTML) 3 Page - National Semiconductor (TI)

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Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
2V
IN+
Differential analog input pins. With a 1.0V reference voltage the
differential full-scale input signal level is 2.0 V
P-P with each
input pin voltage centered on a common mode voltage, V
CM.
The negative input pins may be connected to V
CM for
single-ended operation, but a differential input signal is
required for best performance.
3V
IN
1V
REF
This pin is the reference select pin and the external reference
input.
If (V
A - 0.3V) < VREF < VA, the internal 1.0V reference is
selected.
If AGND < V
REF < (AGND + 0.3V), the internal 0.5V reference
is selected.
If a voltage in the range of 0.4V to (V
A - 0.4V) is applied to this
pin, that voltage is used as the reference.
The full scale differential voltage range is2*V
REF.VREF
should be bypassed to AGND with a 0.1 µF capacitor when an
external reference is used.
31
V
RP
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor. A 10 µF
capacitor should be placed between the V
RP and VRN.
V
RM may be loaded to 1mA for use as a temperature stable
1.5V reference. The remaining pins should not be loaded.
V
RM may be used to provide the common mode voltage, VCM,
for the differential inputs.
32
V
RM
30
V
RN
11
DF/DCS
This is a four-state pin.
DF/DCS = V
A, output data format is offset binary with duty
cycle stabilization applied to the input clock
DF/DCS = AGND, output data format is 2’s complement, with
duty cycle stabilization applied to the input clock.
DF/DCS = V
RM , output data is 2’s complement without duty
cycle stabilization applied to the input clock
DF/DCS = "float", output data is offset binary without duty cycle
stabilization applied to the input clock.
DIGITAL I/O
10
CLK
Digital clock input. The range of frequencies for this input is as
specified in the electrical tables with guaranteed performance
at 20 MHz. The input is sampled on the rising edge.
8PD
PD is the Power Down input pin. When high, this input puts the
converter into the power down mode. When this pin is low, the
converter is in the active mode.
www.national.com
3


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