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ADC12D040CIVSX Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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ADC12D040CIVSX Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 22 page ADC12D040 Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference General Description The ADC12D040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog in- put signals into 12-bit digital words at 40 Megasamples per second (Msps), minimum. This converter uses a differential, pipeline architecture with digital error correction and an on- chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic perfor- mance. Operating on a single 5V power supply, the ADC12D040 achieves 10.9 effective bits at 10 MHz input and consumes just 600 mW at 40 Msps, including the refer- ence current. The Power Down feature reduces power con- sumption to 75 mW. The differential inputs provide a full scale differential input swing equal to 2V REF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs for the two ADCs are available on separate 12-bit buses with an output data format choice of offset binary or 2’s complement. For ease of interface, the digital output driver power pins of the ADC12D040 can be connected to a separate supply voltage in the range of 2.4V to the digital supply voltage, making the outputs compatible with low voltage systems. The ADC12D040’s speed, resolution and single supply op- eration make it well suited for a variety of applications. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40˚C to +85˚C. An evaluation board is available to facilitate the prod- uct evaluation process Features n Binary or 2’s complement output format n Single supply operation n Internal sample-and-hold n Outputs 2.4V to 5V compatible n Power down mode n Pin-compatible with ADC12DL066 n Internal/External Reference Key Specifications n SNR (f IN = 10 MHz) 68 dB (typ) n ENOB (f IN = 10 MHz) 10.9 bits (typ) n SFDR (f IN = 10 MHz) 80 dB (typ) n Data Latency 6 Clock Cycles n Supply Voltage +5V ±5% n Power Consumption, Operating — Operating 600 mW (typ) — Power Down Mode 75 mW (typ) Applications n Ultrasound and Imaging n Instrumentation n Communications Receivers n Sonar/Radar n xDSL n Cable Modems Connection Diagram 20046001 TRI-STATE® is a registered trademark of National Semiconductor Corporation. December 2005 © 2005 National Semiconductor Corporation DS200460 www.national.com |
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