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CY28443OXC-3 Datasheet(PDF) 7 Page - SpectraLinear Inc |
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CY28443OXC-3 Datasheet(HTML) 7 Page - SpectraLinear Inc |
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7 / 23 page  CY28443-3 Rev 1.0, November 20, 2006 Page 7 of 23 1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted 0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted Byte 6: Control Register 6 Bit @Pup Name Description 7 0 TEST_SEL REF/N or Tri-state Select 0 = Tri-state, 1 = REF/N Clock 6 0 TEST_MODE Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Tri-state mode, 5 1 REF1 REF0 Output Drive Strength 0 = Low, 1 = High 4 1 REF0 REF0 Output Drive Strength 0 = Low, 1 = High 3 1 PCI, PCIF and SRC clock outputs except those set to free running SW PCI_STP Function 0=SW PCI_STP assert, 1= SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF, and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF, and SRC outputs will resume in a synchronous manner with no short pulses. 2 HW FSC FSC Reflects the value of the FSC pin sampled on power-up 0 = FSC was low during VTT_PWRGD# assertion 1 HW FSB FSB Reflects the value of the FSB pin sampled on power-up 0 = FSB was low during VTT_PWRGD# assertion 0 HW FSA FSA Reflects the value of the FSA pin sampled on power-up 0 = FSA was low during VTT_PWRGD# assertion Byte 7: Vendor ID Bit @Pup Name Description 7 0 Revision Code Bit 3 Revision Code Bit 3 6 0 Revision Code Bit 2 Revision Code Bit 2 5 0 Revision Code Bit 1 Revision Code Bit 1 4 1 Revision Code Bit 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name Description 7 0 CPU_SS 0:–0.5% (Peak to peak) 1: –1.0% (Peak to peak) 6 0 CPU-DWN_SS 0: Down Spread 1: Center Spread 5 0 RESERVED RESERVED, Set = 0 4 0 RESERVED RESERVED, Set = 0 3 0 RESERVED RESERVED, Set = 0 2 1 48M 48-MHz Output Drive Strength 0 = Low, 1 = High Byte 5: Control Register 5 (continued) Bit @Pup Name Description |
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