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CY28446LFXC Datasheet(PDF) 11 Page - SpectraLinear Inc |
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CY28446LFXC Datasheet(HTML) 11 Page - SpectraLinear Inc |
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11 / 19 page  CY28446 Rev 1.0, November 20, 2006 Page 11 of 19 CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped within two to six CPU clock periods after being sampled by two rising edges of the internal CPUC clock. The final state of all stopped CPU clocks is High/Low when driven, Low/Low when tri-stated CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner, synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. CPU_STP# CPUT CPUC CPUT Internal Tdrive_CPU_STP#,10 ns > 200 mV CPUC Internal Figure 6. CPU_STP# Deassertion Waveform DOT96C DOT96T CPUC(Stoppable) CPUT(Stoppable) CPUC(Free Running CPUT(Free Running PD 1.8 ms CPU_STOP# Figure 7. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven CPU_STP# CPUT CPUC Figure 8. CPU_STP# Assertion Waveform |
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