CY28RS600

Rev 1.0, November 22, 2006

Page 2 of 17

Pin Description

Pin No.

Name

Type

Description

1

VDD_REF

PWR

3.3V power supply for REF, XTAL

2

XIN

I

14.318-MHz Crystal Input

3

XOUT

O

14.318-MHz Crystal Output

4

VDD_48

PWR

3.3V power supply for USB outputs

5,6

USB_48 [1:0]

O, SE 48-MHz clock output. Intel Type-3A buffer

7

VSS_48

GND

Ground for USB outputs

8

VTT_PWRGD#/PD

I

PD

3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,

FS_B, and FS_C inputs. After asserting VTT_PWRGD# (active LOW), this pin

becomes a realtime input for asserting power-down (active HIGH)

9

SCLK

I

SMBus-compatible SCLOCK.This pin has an internal pull-up, but is tri-stated in

power-down.

10

SDATA

I/O

SMBus-compatible SDATA.This pin has an internal pull-up, but is tri-stated in

power-down.

11, 32, 33

CLKREQ#[A:C]

I, SE,

PU

Output Enable control for SRCT/C. Output enable control required by Minicard

specification. This pin has an internal pull-up.

0 = selected SRC output is enabled. 1 = selected SRC output is disabled.

12, 13, 16,

17, 18, 19,

20, 21, 24,

25, 26, 27,

30, 31, 46, 47

SRCT/C[7:0]

O, DIF 100-MHz differential serial reference clock. Intel Type-SR buffer. (10%

overclocking support through SMBUS)

14, 23, 28, 44

VDD_SRC

PWR

3.3V power supply for SRC outputs

15, 22, 29, 45

VSS_SRC

GND

Ground for SRC outputs

34, 35, 36,

37, 40, 41,

42, 43

ATIGT/C[3:0]

O, DIF Differential Selectable serial reference clock. Intel Type-SR buffer.

Includes 50% overclock support through SMBUS

39

VDD_ATIG

PWR

3.3V power supply for ATIG outputs

38

VSS_ATIG

GND

Ground for ATIG outputs

48

VSS_SRC

GND

Ground for SRC outputs

49

VSSA

GND

Analog Ground

50

VDDA

PWR

3.3V Analog Power for PLLs

51, 52, 53,

54, 57, 58

CPUT/C[2:0]

O, DIF Differential CPU clock output.

Intel Type-SR buffer.

55

VSS_CPU

GND

Ground for CPU outputs

56

VDD_CPU

PWR

3.3V power supply for CPU outputs

59

CPU_STP#

I, PU

3.3V LVTTL input.

This pin is used to gate the CPU outputs. CPU outputs are turned off two cycles

after assertion of this pin

60

RESET_IN#

I, PU

3.3V LVTTL Input (Negative Edge Triggered)

When this pin is asserted LOW, all PLLs will transition to a safe default frequency.

This may be the POR defaults or a safe value stored in SMBUS registers.

61

REF2/FSC

I/O, SE 14.318-MHz REF clock output/CPU Frequency Select

Intel Type-5 buffer.

62

REF1/FSB

I/O, SE 14.318-MHz REF clock output/CPU Frequency Select

Intel Type-5 buffer.

63

REF0/FSA

I/O, SE, 14.318-MHz REF clock output/CPU Frequency Select

Intel Type-5 buffer.

64

VSS_REF

PWR

GND for REF, XTAL