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RF5110
Rev A0 DS050318
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Pin
Function
Description
Interface Schematic
1VCC1
Power supply for the pre-amplifier stage and interstage matching. This pin
forms the shunt inductance needed for proper tuning of the interstage
match. Refer to the application schematic for proper configuration. Note
that position and value of the components are important.
See pin 3.
2GND1
Ground connection for the pre-amplifier stage. Keep traces physically short
and connect immediately to the ground plane for best performance. It is
important for stability that this pin has it’s own vias to the groundplane, to
minimize any common inductance.
See pin 1.
3RF IN
RF Input. This is a 50
Ω input, but the actual impedance depends on the
interstage matching network connected to pin 1. An external DC blocking
capacitor is required if this port is connected to a DC path to ground or a
DC voltage.
4GND2
Ground connection for the driver stage. To minimize the noise power at the
output, it is recommended to connect this pin with a trace of about 40mil
to the ground plane. This will slightly reduce the small signal gain, and
lower the noise power. It is important for stability that this pin have it’s own
vias to the ground plane, minimizing common inductance.
See pin 3.
5VCC2
Power supply for the driver stage and interstage matching. This pin forms
the shunt inductance needed for proper tuning of the interstage match.
Please refer to the application schematic for proper configuration, and
note that position and value of the components are important.
6VCC2
Same as pin 5.
7NC
Not connected.
82F0
Connection for the second harmonic trap. This pin is internally connected
to the RF OUT pins. The bonding wire together with an external capacitor
form a series resonator that should be tuned to the second harmonic fre-
quency in order to increase efficiency and reduce spurious outputs.
Same as pin 9.
9RF OUT
RF Output and power supply for the output stage. Bias voltage for the final
stage is provided through this wide output pin. An external matching net-
work is required to provide the optimum load impedance.
10
RF OUT
Same as pin 9.
Same as pin 9.
11
RF OUT
Same as pin 9.
Same as pin 9.
12
RF OUT
Same as pin 9.
13
NC
Not connected.
14
VCC
Power supply for the bias circuits.
15
APC2
Power Control for the output stage. See pin 16 for more details.
See pin 16.
16
APC1
Power Control for the driver stage and pre-amplifier. When this pin is "low,"
all circuits are shut off. A "low" is typically 0.5V or less at room tempera-
ture. A shunt bypass capacitor is required. During normal operation this pin
is the power control. Control range varies from about 1.0V for -10dBm to
2.6V for +35dBm RF output power. The maximum power that can be
achieved depends on the actual output matching; see the application infor-
mation for more details. The maximum current into this pin is 5mA when
V
APC1 =2.6 V, and 0mA when V
APC=0V.
Pkg
Base
GND
Ground connection for the output stage. This pad should be connected to
the ground plane by vias directly under the device. A short path is required
to obtain optimum performance, as well as to provide a good thermal path
to the PCB for maximum heat dissipation.
GND1
RF IN
VC C1
From Bias
Stages
GND2
VCC2
From Bias
Stages
GND
PCKG BASE
RF OUT
From Bias
Stages
GN D
VC C
To R F
S t a ges
GN D
APC
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