9

FN6651.0

February 12, 2008

TABLE 2. HOST TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING

PARAMETER

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

Bit Time

x = 0.5, 1, 2, or 4

173.6/x

µs

Deglitch period

tg

PW (Pulse Width) less than this will result in a frame error

0.124

‘1’ pulse width

PW in this range will be interpreted as a ‘1’ code

0.227

0.453

‘0’ pulse width

PW in this range will be interpreted as a ‘0’ code

0.591

0.824

‘break’ time

PW in this range will be interpreted as a ‘break’ command

1

100

NOTE: Unless otherwise stated, all pulse width (PW) referenced are with respect to an active-low pulse.

TABLE 3. DEVICE TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING

PARAMETER

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

Bit Time

x = 0.5, 1, 2, or 4

164.2/x

172.8/x

181.4/x

µs

‘1’ pulse width

‘1’ code transmit pulse width

0.304

‘0’ pulse width

‘0’ code transmit pulse width

0.696

‘break’ time

PW in this range will be interpreted as a ‘break’ command

1.391

FIGURE 7. THE CIRCUIT MODEL FOR THE XSD SERIAL BUS

V

DDD

V

DDH

R

PU

TX

RX

TX

RX

HOST

DEVICE

Open-Drain

Port Pin

1.5

μA

ESD

Diode

ESD

Diode

6pF

OPEN-DRAIN

PORT PIN

ESD

DIODE

ESD

DIODE

FIGURE 8. THE BUS SIGNAL TIMING DIAGRAM

glitch

t1

t0

tb

tg

XSD

10

Break

BT

GLITCH

BREAK

BT

FIGURE 9. THE 16-BIT INSTRUCTION FRAME FIELD DEFINITION

0

15

OPCODE

BANK

ADDRESS

BYTES

CS

0

15

OPCODE

BANK

ADDRESS

BYTES

CS

0

15

OPCODE

BANK

ADDRESS

BYTES

CS

BYTES

ADDRESS

BANK

OPCODE CS

15

0

ISL9206A