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EVB71122

300 to 930MHz Receiver

Evaluation Board Description

39012 71122 01

Page 5 of 32

EVB Description

Rev. 001

Sept/06

1.3

Block Diagram

Fig. 1:

MLX71122 block diagram

The MLX71122 receiver IC consists of the following building blocks:

•

PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2,

parts of the PLL SYNTH are the voltage-controlled oscillator (VCO), the feedback dividers N/A and R,

the phase-frequency detector (PFD), the charge pump (CP) and the crystal-based reference oscillator

(RO)

•

Low-noise amplifier (LNA) for high-sensitivity RF signal reception

•

First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)

•

Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF

•

IF Filter (IFF) with a 2MHz center frequency and a 230kHz 3dB bandwidth

•

IF amplifier (IFA) to provide a large amount of voltage gain and an RSSI signal output

•

FSK demodulator (FSK DEMOD)

•

Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively

•

Positive (PKDET+) and negative (PKDET-) peak detectors

•

Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak

detector data slicer

•

Control logic with 3-wire bus serial programming interface (SPI)

•

Biasing circuit with modes control

For more detailed information, please refer to the latest MLX71122 data sheet revision.

FSK

DEMOD

Control

Logic

SLCSEL

BIAS

OA2

DFO

OA1

PKDET+

PKDET

_

SLC

PDP

PDN

DTAO

29

27

26

30

25

32

28

22

20

16

21

17

18

19

7

10

200k

200k

SW2

SW1

ASK

FSK

LNA

LNAI

4

3

31

2

1

14

11

23

R

counter

N / A

counter

PFD

VCO

LF

CP

RO

LO2DIV

9

IFA

LO2

IF2

IF1

LO1

MIX1

MIX2

IFF

5

6

8

15

24

TNK1

TNK2

12 13