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ICS950910 Datasheet(PDF) 4 Page - Integrated Device Technology |
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ICS950910 Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 21 page 4 Integrated Circuit Systems, Inc. ICS950910 0735B—09/21/07 General Description The ICS950910 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with PC133 or DDR memory. The ICS950910 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment. Block Diagram FBOUT VDD GND 55 2 Xtal, Ref 5 9 AGP [0:2], CPU digital, CPU PLL 16 13 PCI [0:5], PCI_F outputs 22 19 48MHz, Fix Digital, Fix Analog 23 24 Master clock, CPU Analog 34, 40 33, 39 DDR/SDR outputs 50 47 2.5V CPUT/C_CS output 51 54 3.3V CPUT/C & CPUOD_T/C Pin Number Description Power Groups |
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