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ICS844071AG Datasheet(PDF) 11 Page - Integrated Device Technology

Part # ICS844071AG
Description  FEMTOCLOCKS??CRYSTAL-TO-LVDS CLOCK GENERATOR
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS844071AG Datasheet(HTML) 11 Page - Integrated Device Technology

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ICS844071
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
IDT™ / ICS™ LVDS CLOCK GENERATOR
11
ICS844071AG SEPTEMBER 26, 2007
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844071.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS844071 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.63V * (135mA + 12mA) = 533.61mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming a moderate
air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.533W * 90.5°C/W = 118.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection
θ
JA by Velocity
Meters per Second
01
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5
89.8


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