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ICS844021I-01 Datasheet(PDF) 9 Page - Integrated Device Technology

Part # ICS844021I-01
Description  FEMTOCLOCKS??CRYSTAL-TO-LVDS CLOCK GENERATOR
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS844021I-01 Datasheet(HTML) 9 Page - Integrated Device Technology

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IDT/ ICSLVDS CLOCK GENERATOR
9
ICS844021BGI-01 REV. C SEPTEMBER 27, 2007
ICS844021I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844021I-01
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844021I-01 is the sum of the core power plus the analog plus the power dissipated in the
load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)
MAX
= V
DD_MAX
* (I
DD_MAX
+ I
DDA_MAX
) = 3.465V * (55mA + 8mA) = 218.3mW
2.
Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.218W * 129.5°C/W = 113.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE
θθθθθ
JA
FOR
8-LEAD TSSOP, FORCED CONVECTION
θθθθθ
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
125.5°C/W
123.5°C/W


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