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ICS843021AGI-01LF Datasheet(PDF) 7 Page - Integrated Device Technology |
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ICS843021AGI-01LF Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 15 page  ICS843021I-01 FEMTOCLOCKS™CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR IDT™ / ICS™ 3.3V , 2.5V LVPECL CLOCK GENERATOR 7 ICS843021AGI-01 REV. A DECEMBER 3, 2007 Application Information Crystal Input Interface The ICS843021I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. Figure 1. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 2. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 Ω applications, R1 and R2 can be 100 Ω. This can also be accomplished by removing R1 and making R2 50 Ω. Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_IN XTAL_OUT X1 18pF Parallel Crystal C1 27p C2 27p XTAL_IN XTAL_OUT Ro Rs Zo = Ro + Rs 50 Ω 0.1µf R1 R2 VCC VCC |
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