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PACKAGE DISSIPATION RATINGS

THERMAL CHARACTERISTICS

0

1

0

1

OUT 0

OUT 1

EN 0

EN 1

SEL 1

SEL 0

IN 0

IN 1

SN65LVCP23

SLLS554E – NOVEMBER 2002 – REVISED MAY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGE DESIGNATOR

SYMBOLIZATION

SOIC

SN65LVCP23D

LVCP23

TSSOP

SN65LVCP23PW

LVCP23

(1)

Add the suffix R for taped and reeled carrier

CIRCUIT

PACKAGE

BOARD MODEL

POWER RATING

POWER RATING

SOIC (D)

1361 mW

13.9 mW/°C

544 mW

TSSOP (PW)

1074 mW

10.7 mW/°C

430 mW

(1)

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

(2)

In accordance with the High-K thermal metric definitions of EIA/JESD51-7.

PARAMETER

TEST CONDITIONS

VALUE

UNITS

D

15.7

°C/W

θ

JB

Junction-to-board thermal resistance

PW

22.1

°C/W

D

26.1

°C/W

θ

JC

Junction-to-case thermal resistance

PW

17.3

°C/W

Typical

165

mW

Device power dissipation

Maximum

234

mW

FUNCTIONAL BLOCK DIAGRAM

2

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