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SN65LVCP23DRG4 Datasheet(PDF) 2 Page - Texas Instruments |
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SN65LVCP23DRG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 19 page www.ti.com PACKAGE DISSIPATION RATINGS THERMAL CHARACTERISTICS 0 1 0 1 OUT 0 OUT 1 EN 0 EN 1 SEL 1 SEL 0 IN 0 IN 1 SN65LVCP23 SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGE DESIGNATOR PART NUMBER(1) SYMBOLIZATION SOIC SN65LVCP23D LVCP23 TSSOP SN65LVCP23PW LVCP23 (1) Add the suffix R for taped and reeled carrier CIRCUIT TA ≤ 25°C DERATING FACTOR(1) TA = 85°C PACKAGE BOARD MODEL POWER RATING ABOVE TA = 25°C POWER RATING SOIC (D) High-K(2) 1361 mW 13.9 mW/°C 544 mW TSSOP (PW) High-K(2) 1074 mW 10.7 mW/°C 430 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. (2) In accordance with the High-K thermal metric definitions of EIA/JESD51-7. PARAMETER TEST CONDITIONS VALUE UNITS D 15.7 °C/W θ JB Junction-to-board thermal resistance PW 22.1 °C/W D 26.1 °C/W θ JC Junction-to-case thermal resistance PW 17.3 °C/W Typical VCC = 3.3 V, TA = 25°C, 2 Gbps 165 mW PD Device power dissipation Maximum VCC = 3.6 V, TA = 85°C, 2 Gbps 234 mW FUNCTIONAL BLOCK DIAGRAM 2 Submit Documentation Feedback |
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