ICS252

FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER

EPROM CLOCK SYNTHESIZER

IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 2

ICS252

REV E 082007

Pin Assignment

8-pin (150 mil) SOIC

Output Clock Selection Table

Pin Descriptions

External Components

The ICS252 requires a minimum number of external

components for proper operation.

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50

Ω trace (a commonly

used trace impedance), place a 33

Ω resistor in series with

the clock line, as close to the clock output pin as possible.

The nominal impedance of the clock output is 20

Ω.

Decoupling Capacitor

As with any high-performance mixed-signal IC, the ICS252

must be isolated from system power supply noise to perform

optimally.

A decoupling capacitor of 0.01µF must be connected

between VDD and the PCB ground plane.

Crystal Load Capacitors

The device crystal connections should include pads for

small capacitors from X1 to ground and from X2 to ground.

These capacitors are used to adjust the stray capacitance

of the board to match the nominally required crystal load

capacitance. Because load capacitance can only be

increased in this trimming process, it is important to keep

stray capacitance to a minimum by using very short PCB

traces (and no vias) been the crystal and device. Crystal

capacitors must be connected from each of the pins X1 and

X2 to ground.

Example: For a crystal with a 16 pF load capacitance, each

crystal capacitor would be 20 pF [(16-6) x 2 = 20].

PCB Layout Recommendations

For optimum device performance and lowest output phase

X 1 /IC L K

VD D

G N D

SEL

CL K 2

CL K 1

X2

1

2

3

4

8

7

6

5

PD T S

SEL

CLK1 (MHz)

CLK2 (MHz)

Spread

Percentage

0

User

Configurable

User

Configurable

User

Configurable

1User

Configurable

User

Configurable

User

Configurable

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

SEL

Input

Select pin for frequency selection on CLK1 and CLK2. Internal pull-up resistor.

2

VDD

Power

Connect to +3.3 V.

3

X1/ICLK

XI

Connect this pin to a crystal or external clock input.

4

X2

XO

Connect this pin to a crystal, or float for clock input.

5

CLK1

Output

Clock1 output. Weak internal pull-down, low when power down.

6

CLK2

Output

Clock2 output. Weak internal pull-down, low when power down.

7

GND

Power

Connect this to ground.

8PDTS

Input

Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up

resistor. The pin must be tied either directly or through the external resistor to

VDD ro GND. External resistor value must be less than 15kOhm.