Electronic Components Datasheet Search |
|
IDT5V9885 Datasheet(PDF) 7 Page - Integrated Device Technology |
|
IDT5V9885 Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 37 page 7 INDUSTRIALTEMPERATURERANGE IDT5V9885 3.3V EEPROMPROGRAMMABLECLOCKGENERATOR Feedback-Divider N[11:0]andA[3:0]arethebitsusedtoprogramthefeedback-dividerforPLL0(N0andA0)andPLL1(N1andA1). Ifspreadspectrumgenerationisenabled foreitherPLL0orPLL1,thenthe SS_OFFSET[5:0]bits(0x61,0x69)wouldbefactoredintotheoverallfeedbackdividervalue. SeetheSPREADSPECTRUM GENERATIONsectionformoredetailsonhowtoconfigurePLL0andPLL1whenspreadspectrumisenabled. ThetwoPLLscanalsobeconfiguredforfractional divideratios. SeeFRACTIONALDIVIDERformoredetails. ForPLL2,onlytheN[11:0]bits(N2)areusedtoprogramitsfeedbackdividerandthereisnospread spectrum generation and fractional divides capability. The12-bit feedback-divider integer values range from 1 to 4095. The following equations govern how the feedback divider value is set. Note that the equations are different for PLL0/PLL1 and PLL2 PLL0 and PLL1: M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] * 1/64 (Eq. 3) M = 2*N[11:0] + A[3:0] + 1 (spread spectrum disabled) (Eq. 4) A[3:0] = 0000 = -1 = 0001 = 1 = 0010 = 2 = 0011 = 3 . . . = 1111 = 15 Note: A[3:0] < (N[11:0] - 5), must be met when using A. N cannot be programmed with a value of 4, 8, or 16 when using A. PLL2: M = N[11:0] (Eq. 5) The user can achieve an even or odd integer divide ratio for both PLL0 and PLL1 by setting the A[3:0] bits accordingly and disabling the spread spectrum. AfractionaldividecanalsobesetforPLL0andPLL1byusingtheA[3:0]bitsinconjunctionwiththeSS_OFFSET[5:0]bits,whichisdetailedintheFRACTIONAL DIVIDERsection. NotethattheVCOhasafrequencyrangeof10MHzto1200MHz. To maintainlowjitter,itisbesttomaximizetheVCOfrequency. Forexample, if the reference clock is 100MHz and a 200MHz clock is required, to achieve the best jitter performance, multiply the 100MHz by 12 to get the VCO running at thehighestpossiblefrequencyof1200MHzandthendivideitdowntoget200MHz. Orifthereferenceclockis25MHzand20MHzistherequiredclock,multiply the 25MHz by 40 to get the VCO running at 1000MHz and then divide it down to get 20MHz. If N is set to '0x00', the VCO will slew to the minimum frequency. Post-Divider Q[9:0] are the bits used to program the 10-bit post-dividers on output banks OUT2-6. OUT1 bank does not have a 10-bit post-divider or any other post- divide along its path. The 10-bit post-dividers will divide down the output banks' frequency with integer values ranging from 1 to 1023. There is the option to choose between disabling the post-divider, utilizing a div/1, a div/2, or the 10-bit post-divider by using the PM[1:0] bits. . Each bank, except for OUT1, has a set of PM bits. When disabling the post-divider, no clock will appear at the outputs, but will remain powered on. The values are listed in the table below. PM[1:0] P Post-Divider 00 disabled 01 div/1 10 div/2 11 Q[9:0] + 2 (Eq. 6) 00 01 10 11 /2 / (Q+2) PM[1:0] /2 To Outputs VCO P Post-Divider Diagram |
Similar Part No. - IDT5V9885 |
|
Similar Description - IDT5V9885 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |