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ETC5067 Datasheet(PDF) 8 Page - STMicroelectronics |
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ETC5067 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 18 page All TIMING SPECIFICATIONS Symbol Parameter Min. Typ. Max. Unit 1/tPM Frequency of master clocks MCLKX and MCLKR Depends on the device used and the BCLKR/CLKSEL Pin 1.536 2.048 1.544 MHz tWMH Width of Master Clock High MCLKX and MCLKR 160 ns tWML Width of Master Clock Low MCLKX and MCLKR 160 ns tRM Rise Time of Master Clock MCLKX and MCLKR 50 ns tFM Fall Time of Master Clock MCLKX and MCLKR 50 ns tPB Period of Bit Clock 485 488 15.725 ns tWBH Width of Bit Clock High (VIH = 2.2 V) 160 ns tWBL Width of Bit Clock Low (VIL = 0.6 V) 160 ns tRB Rise Time of Bit Clock (tPB = 488 ns) 50 ns tFB Fall Time of Bit Clock (tPB = 488 ns) 50 ns tSBFM Set-up time from BCLKX high to MCLKX falling edge. (first bit clock after the leading edge of FSX) 100 ns tHBF Holding Time from Bit Clock Low to the Frame Sync (long frame only) 0ns tSFB Set-up Time from Frame Sync to Bit Clock (long frame only) 80 ns tHBFI Hold Time from 3rd Period of Bit Clock FSX or FSR Low to Frame Sync (long frame only) 100 ns tDZF Delay Time to valid data from FSX or BCLKX, whichever comes later and delay time from FSX to data output disabled (CL = 0 pF to 150 pF) 20 165 ns tDBD Delay Time from BCLKX high to data valid (load = 150 pF plus 2 LSTTL loads) 0 150 ns tDZC Delay Time from BCLKX low to data output disabled 50 165 ns tSDB Set-up Time from DR valid to BCLKR/X low 50 ns tHBD Hold Time from BCLKR/X low to DR invalid 50 ns tHOLD Holding Time from Bit Clock High to Frame Sync (short frame only) 0 ns tSF Set-up Time from FSX/R to BCLKX/R Low (short frame sync pulse) - Note 1 80 ns tHF Hold Time from BCLKX/R Low to FSX/R Low (short frame sync pulse) - Note 1 100 ns tXDP Delay Time to TSX low (load = 150 pF plus 2 LSTTI loads) 140 ns tWFL Minimum Width of the Frame Sync Pulse (low level) (64 bit/s operating mode) 160 ns Note : 1.For short frame sync timing. FSX and FSR must go high while their respective bit clocks are high. Figure 1 : 64 k bits/s TIMING DIAGRAM. (see next page for complete timing) ETC5064 - ETC5064-X - ETC5067 - ETC5067-X 8/18 |
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