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ESDA25SC6 Datasheet(PDF) 3 Page - STMicroelectronics |
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ESDA25SC6 Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 7 page ESDAxxSC5 / ESDAxxSC6 3/7 The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula: VCL =VBR +RdIPP Where Ipp is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20 µs and 10/1000µs surges. 2.5 µs duration measurement wave. As the value of the dynamic resistance remains stable for a surge duration lower than 20 µs, the 2.5 µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd. CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE 2µs tp = 2.5µs t I Ipp |
Similar Part No. - ESDA25SC6 |
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Similar Description - ESDA25SC6 |
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