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SN74LVT8986PM Datasheet(PDF) 4 Page - Texas Instruments |
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SN74LVT8986PM Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 54 page  www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) SN54LVT8986 ,, SN74LVT8986 3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS759E – OCTOBER 2002 – REVISED MAY 2007 The address (A9–A0) inputs to the LASP are used to identify the LASP. The position (P2–P0) inputs to the LASP are used to identify the position of the LASP within a cascade chain when multiple LASPs are cascaded. Up to 8 LASPs can be cascaded to link a maximum of 24 secondary scan paths to 1 primary scan path. In a system, primary-to-secondary connection is based on linking shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states, other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address, position the LASP in the cascade chain that is being configured, and configuration of secondary TAPs via a serial bit-pair signaling scheme. When address and position bits received serially at PTDI match those at the parallel address (A9–A0) inputs and position (P2–P0) inputs respectively, the secondary TAPs are configured per the configuration bits received during the linking shadow protocol, then LASP serially retransmits the entire linking shadow protocol as an acknowledgment and assumes the connected (ON) status. If the received address or position does not match that at the address (A9–A0) inputs or position (P2–P0) inputs, the LASP immediately assumes the disconnected (OFF) status, without acknowledgment. The LASP also supports three dedicated addresses that can be received globally (that is, to which all LASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the LASP to disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving LASPs. The DSA is especially useful when the secondary TAPs of multiple LASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the LASP to assume the reset condition. Receipt of the test-synchronization address (TSA) causes the LASP to assume a connect status (MULTICAST) in which PTDO is at high impedance, but the configuration of the secondary TAPs are maintained to allow simultaneous operation of the secondary TAPs of multiple LASPs. This is useful for multicast TAP-state movement, simultaneous test operation, such as in Run-Test/Idle state, and scanning of common test data into multiple like scan chains. The MULTICAST status may also be useful for concurrent in-system programming (ISP) of common modules. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states. Refer to Table 9 for different address mapping. Alternatively, primary-to-secondary connection can be selected by asserting a low level at the bypass (BYP5) input. The remaining bypass (BYP4–BYP0) inputs are used for configuring the secondary TAPs as shown in Table 1 and Table 2. This operation is asynchronous to PTCK and is independent of PTRST and/or power-up reset. This bypassing feature is especially useful in the board-test environment because it allows board-level automated test equipment (ATE) to treat the LASP as a simple transceiver. When BYP5 is high, the LASP is free to respond to linking shadow protocols. Otherwise, when BYP5 is low, linking shadow protocols are ignored. Whether the connected status is achieved by use of linking shadow protocol or by use of bypass inputs, this status is indicated by a low level at the connect (CON2–CON0) outputs. Likewise, when the secondary TAP is disconnected from the primary TAP, the corresponding CON output is high. Each secondary TAP has a pass-through input and output consisting of SX2–SX0 and SY2–SY0, respectively. Similarly, the primary TAP also has a pass-through input and output consisting of PX and PY, respectively. Pass-through input PX drives the SY outputs of the secondary TAPs that are connected to the primary TAP. Disconnected secondary TAPs have their SY outputs at high impedance. Pass-through inputs SY2–SY0 of the connected secondary TAPs are logically ANDed and drive the PY output. Refer to Table 4-7 for pass-through input/output operation. 4 Submit Documentation Feedback |
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