EDE5108AJSE-8E-E datasheet(9/77 Pages) ELPIDA

Part #	EDE5108AJSE-8E-E

Description	512M bits DDR2 SDRAM

Download	77 Pages

Scroll/Zoom	100%

Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

Logo

9 / 77 page

EDE5104AJSE, EDE5108AJSE, EDE5116AJSE

Data Sheet E1043E40 (Ver. 4.0)

9

×4

×8

×16

Parameter

Symbol

Grade

max.

Unit

Test condition

Auto-refresh current

IDD5

-8E

-6E

105

100

105

100

105

100

mA

tCK = tCK (IDD);

Refresh command at every tRFC (IDD)

interval;

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are

SWITCHING;

Data bus inputs are SWITCHING

Self-refresh current

IDD6*

7

6

mA

Self Refresh Mode;

CK and /CK at 0V; CKE

≤ 0.2V;

Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

Operating current

(Bank interleaving)

IDD7

-8E

-6E

160

150

160

150

240

230

mA

all bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD),

AL = tRCD (IDD)

−1

× tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD),

tRRD = tRRD(IDD), tRCD = 1

× tCK (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are STABLE during

DESELECTs; Data pattern is same as IDD4W

Notes: 1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate is specified by AC Input Test Condition.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS.

IDD values must be met with all

combinations of EMRS bits 10 and 11.

5. Definitions for IDD

L is defined as VIN

≤ VIL (AC) (max.)

H is defined as VIN

≥ VIH (AC) (min.)

STABLE is defined as inputs stable at an H or L level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between H and L every other clock cycle (once per two clocks) for address and control

signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals

not including masks or strobes.

6. Refer to AC Timing for IDD Test Conditions.

7. When TC

≥ +85°C, IDD6 must be derated by 80%.

IDD6 will increase by this amount if TC

≥ +85°C and double refresh option is still enabled.

AC Timing for IDD Test Conditions

For purposes of IDD testing, the following parameters are to be utilized.

DDR2-800

DDR2-667

Parameter

5-5-5

Unit

CL (IDD)

5

tCK

tRCD (IDD)

12.5

15

ns

tRC (IDD)

57.5

60

ns

tRRD (IDD)-

×4/×8

7.5

ns

tRRD (IDD)-

×16

10

ns

tCK (IDD)

2.5

3

ns

tRAS (min.)(IDD)

45

ns

tRAS (max.)(IDD)

70000

ns

tRP (IDD)

12.5

15

ns

tRFC (IDD)

105

ns

Similar Part No. - EDE5108AJSE-8E-E

Manufacturer	Part #	Datasheet	Description
Elpida Memory	EDE5108AJBG	620Kb / 77P	512M bits DDR2 SDRAM
	EDE5108AJBG-1J	783Kb / 77P	512M bits DDR2 SDRAM
	EDE5108AJBG-1J-E	783Kb / 77P	512M bits DDR2 SDRAM
	EDE5108AJBG-6E-E	620Kb / 77P	512M bits DDR2 SDRAM
	EDE5108AJBG-6E-E	814Kb / 77P	512M bits DDR2 SDRAM

More results

Similar Description - EDE5108AJSE-8E-E

Manufacturer	Part #	Datasheet	Description
Elpida Memory	EDE5108AHBG	788Kb / 75P	512M bits DDR2 SDRAM
	EDE5104AGSE	592Kb / 74P	512M bits DDR2 SDRAM
	EDE5108AJBG	620Kb / 77P	512M bits DDR2 SDRAM
	EDE5108AESK	680Kb / 65P	512M bits DDR2 SDRAM
	EDE5104AHSE	562Kb / 69P	512M bits DDR2 SDRAM
	EDE5104ABSE	697Kb / 66P	512M bits DDR2 SDRAM
	EDE5108AHSE	880Kb / 81P	512M bits DDR2 SDRAM
	EDE5104AJBG	814Kb / 77P	512M bits DDR2 SDRAM
	EDE5132BABG	756Kb / 74P	512M bits DDR2 SDRAM
	EDE5132AABG	735Kb / 74P	512M bits DDR2 SDRAM

More results

EDE5108AJSE-8E-E Datasheet(PDF) 9 Page - Elpida Memory

EDE5108AJSE-8E-E Datasheet(HTML) 9 Page - Elpida Memory

Similar Part No. - EDE5108AJSE-8E-E

Similar Description - EDE5108AJSE-8E-E

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL