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SST29LE010A-90-4C-EH Datasheet(PDF) 5 Page - Silicon Storage Technology, Inc |
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SST29LE010A-90-4C-EH Datasheet(HTML) 5 Page - Silicon Storage Technology, Inc |
5 / 26 page 5 © 1999 Silicon Storage Technology, Inc. 303-01 2/99 1 Megabit Page Mode EEPROM SST29EE010A / SST29LE010A / SST29VE010A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions A16-A7 Row Address Inputs To provide memory addresses. Row addresses define a page for a write cycle. A6-A0 Column Address Column Addresses are toggled to load page data. Inputs DQ7-DQ0 Data Input/output To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the write operations Vcc Power Supply To provide 5-volt supply (± 10%) for the SST29EE010A, 3-volt supply (3.0-3.6V) for the SST29LE010A and 2.7-volt supply (2.7-3.6V) for the SST29VE010A Vss Ground NC No Connection Unconnected pins. 303 PGM T2.0 A11 A9 A8 A13 A14 NC WE# VCC NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 303 ILL F01.0 Standard Pinout Top View Die Up 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29 28 27 26 25 24 23 22 21 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 4 3 2 1 32 31 30 32-Lead PLCC Top View 32-Pin PDIP Top View 303 ILL F02.0 14 15 16 17 18 19 20 NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 |
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