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SN65HVD3082EDG4 Datasheet(PDF) 11 Page - Texas Instruments |
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SN65HVD3082EDG4 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 23 page SN65HVD3082E,SN75HVD3082E SN65HVD3085E,SN65HVD3088E SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005 www.ti.com 11 DGK Package THERMAL CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ΘJA Junction-to-ambient thermal resistance(1) Low-k(2) board, no air flow 266 °C/W ΘJA Junction-to-ambient thermal resistance(1) High-k(3) board, no air flow 180 °C/W ΘJB Junction-to-board thermal resistance High-k(3) board, no air flow 108 °C/W ΘJC Junction-to-case thermal resistance 66 °C/W P(AVG) Average power dissipation RL = 54 Ω, Input to D is a 200 kbps 50% duty cycle square wave HVD3082E 203 mW P(AVG) Average power dissipation L 50% duty cycle square wave Vcc at 5.5 V, TJ = 130°C HVD3082E 203 mW P(AVG) Average power dissipation RL = 54 Ω, Input to D is a 1 Mbps 50% duty cycle square wave Vcc at 5.5 V, TJ = 130°C HVD3085E 205 mW P(AVG) Average power dissipation RL = 54 Ω, Input to D is a 20 Mbps 50% duty cycle square wave Vcc at 5.5 V, TJ = 130°C HVD3088E 276 mW TA Ambient air temperature High k board model −40 93 °C TA Ambient air temperature Low k board model −40 75 °C TSD Thermal shut-down junction temperature 165 °C (1) See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter. (2) JESD51-3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (3) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages |
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