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M24M01-R Datasheet(PDF) 6 Page - STMicroelectronics |
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M24M01-R Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 30 page Description M24M01-R 6/30 1 Description The M24M01-R is an I2C-compatible electrically erasable programmable memory (EEPROM) device organized as 128 Kb × 8 bits. The I2C bus is a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition. The M24M01-R behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are generated by the bus master and initiated by a Start condition, followed by the device select code, address bytes and data bytes. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. In order to meet environmental requirements, ST offers the M24M01-R in ECOPACK® packages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram Table 1. Signal names Signal name Function Direction E1, E2 Chip Enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage VSS Ground AI13415b SDA VCC M24M01-R WC SCL VSS 2 E1-E2 |
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