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PACKAGE DISSIPATION RATINGS

THERMAL CHARACTERISTICS

0

1

0

1

OUT 0

OUT 1

EN 0

EN 1

SEL 1

SEL 0

IN 0

IN 0

IN 1

SN65LVCP22

SLLS553B – NOVEMBER 2002 – REVISED JUNE 2003

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGE DESIGNATOR

SYMBOLIZATION

SOIC

SN65LVCP22D

LVCP22

TSSOP

SN65LVCP22PW

LVCP22

(1)

Add the suffix R for taped and reeled carrier

CIRCUIT BOARD

PACKAGE

MODEL

POWER RATING

POWER RATING

SOIC (D)

1361 mW

13.9 mW/

°C

544 mW

TSSOP (PW)

1074 mW

10.7 mW/

°C

430 mW

(1)

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

(2)

In accordance with the High-K thermal metric definitions of EIA/JESD51-7.

PARAMETER

TEST CONDITIONS

VALUE

UNITS

D

11.2

θ

JB

Junction-to-board thermal resistance

°C/W

PW

18.4

D

23.7

θ

JC

Junction-to-case thermal resistance

°C/W

PW

16.0

Typical

198

Device power dissipation

mW

Maximum

313

FUNCTION TABLE

SEL0

SEL1

OUT0

OUT1

FUNCTION

0

0

IN0

IN0

1:2 Splitter

0

1

IN0

IN1

Repeater

1

0

IN1

IN0

Switch

1

1

IN1

IN1

1:2 Splitter

FUNCTIONAL BLOCK DIAGRAM

2

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