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ADS6143IRHBR Datasheet(PDF) 10 Page - Texas Instruments |
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ADS6143IRHBR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 68 page www.ti.com ADS6145, ADS6144 ADS6143, ADS6142 SLWS198A – JULY 2007 – REVISED OCTOBER 2007 TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued) For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data sheet. ADS6145 ADS6144 ADS6143 ADS6142 FS = 125 MSPS FS = 105 MSPS FS = 80 MSPS FS = 65 MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Clock Input clock rising edge tPDI propagation zero-cross to 50% of 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 ns delay CLKOUT rising edge Duty cycle of output Output clock clock (CLKOUT), 45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55% duty cycle 10 ≤ Fs ≤ 125 MSPS Rise time measured from 20% to 80% of Data rise DRVDD, tr time, Fall time measured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns tf Data fall from 80% to 20% of time DRVDD, 1 ≤ Fs ≤ 125 MSPS Rise time measured from 20% to 80% of tCLKRI Output clock DRVDD, SE rise time, Fall time measured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns tCLKFA Output clock from 80% to 20% of LL fall time DRVDD, 1 ≤ Fs ≤ 125 MSPS 10 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6145, ADS6144 ADS6143, ADS6142 |
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