IP175A LF
Preliminary Data Sheet
11/60
February 20, 2006
Copyright © 2004, IC Plus Corp.
IP175A LF-DS-R08
Pin Descriptions (continued)
Pin no.
Label
Type
Description
External MII0 interface (PHY mode, MII0_MAC_MOD=0, P4MII_SNI=0)
81
MII0_TXCLK
O
MII transmit clock
80, 79,
78, 77
TXD0_0, TXD0_1,
TXD0_2, TXD0_3
IPL2
MII transmit data
It is sampled at the rising edge of MII0_TXCLK.
76
TXEN0
IPL2
MII transmit enable
It is used to frame TXD0[3:0]. It is sampled at the rising edge of
MII0_TXCLK.
90
COL0
O
MII collision
It is active when port 4 of switch controller is set to be half duplex
and a collision event happens.
84
RXDV0
O
MII receive data valid
It is used to frame RXD0[3:0]. It is sent out at the falling edge of
MII0_TXCLK.
88, 87,
86, 85
RXD0_0, RXD0_1,
RXD0_2, RXD0_3
O
MII receive data
It is sent out at the falling edge of MII0_TXCLK.
89
MII0_RXCLK
O
MII receive clock
There is no clock output in this mode.
Pin no.
Label
Type
Description
External MII0 interface (MAC mode, MII0_MAC_MOD=1, P4MII_SNI=0)
81
MII0_TXCLK
I
MII transmit clock
It is an input clock and it is connected to MII_TXCLK of external PHY.
80, 79,
78, 77
TXD0_0, TXD0_1,
TXD0_2, TXD0_3
O
MII transmit data
It is connected to MII_TXD of external PHY. It is sent out at the
rising edge of MII0_TXCLK.
76
TXEN0
O
MII transmit enable
It is an output signal and is connected to MII_TXEN of external
PHY. It is sent out at the rising edge of MII0_TXCLK.
90
COL0
IPL2
MII collision
It is an input signal and is connected to the MII_COL of external PHY.
84
RXDV0
I
MII receive data valid
It is an input signal and is connected to the MII_RXDV of
external PHY. RXDV0 is used to frame RXD0[3:0].
88, 87,
86, 85
RXD0_0, RXD0_1,
RXD0_2, RXD0_3
I
Receive data
It is NRZ data and is connected MII_RXD[3:0] of external PHY. It
is received at the rising edge of MII0_RXCLK.
89
MII0_RXCLK
I
MII receive clock
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