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RECOMMENDED OPERATING CONDITIONS

ADS5237

SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007

ADS5237

PARAMETER

MIN

TYP

MAX

UNIT

SUPPLIES AND REFERENCES

Analog supply voltage, AVDD

3.0

3.3

3.6

V

Output driver supply voltage, VDRV

3.0

3.3

3.6

V

1.875

2.0

2.05

V

0.95

1.0

1.125

V

(1)

V

0.75

1.0

1.1

V

V

CLOCK INPUT AND OUTPUTS

ADCLK Input sample rate

PLL enabled (default)

20

65

MSPS

PLL disabled

2

MSPS

ADCLK duty cycle

PLL enabled (default)

45

55

MSPS

Low-level voltage clock input

0.6

V

High-level voltage clock input

2.2

V

–40

+85

°C

Thermal characteristics:

42.8

°C/W

18.7

°C/W

(1)

(2)

When the PLL is disabled, the clock duty cycle needs to be controlled well, especially at higher speeds. A 45%–55% duty cycle variation

is acceptable up to a frequency of 30MSPS. If the device needs to be operated in the PLL disabled mode beyond 30MSPS, then the

duty cycle needs to be maintained within a 48%–52% duty cycle.

Copyright © 2007, Texas Instruments Incorporated

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