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ADS5237IPAG Datasheet(PDF) 8 Page - Texas Instruments |
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ADS5237IPAG Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 29 page  www.ti.com ADS5237 SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007 TIMING CHARACTERISTICS (continued) Typical values at TA = +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% duty cycle, and total capacitive loading = 10pF, unless otherwise noted. PARAMETER MIN TYP MAX UNITS 50MSPS With PLL ON tA Aperture delay 2.1 ns Aperture jitter 1.0 ps t1 Data setup time 3.2 4.5 ns t2 Data hold time 10 11 ns tD Data latency 6 Clocks tDR, tDF Data rise/fall time 0.5 2 3 ns Data valid (DV) duty cycle 30 40 55 % tDV Input clock rising to DV fall edge 11.5 13.5 15.5 ns 40MSPS With PLL ON tA Aperture delay 2.1 ns Aperture jitter 1.0 ps t1 Data setup time 3.7 5.5 ns t2 Data hold time 11.5 13.5 ns tD Data latency 6 Clocks tDR, tDF Data rise/fall time 0.5 2 3 ns Data valid (DV) duty cycle 30 40 55 % tDV Input clock rising to DV fall edge 13.5 16 18.5 ns 30MSPS With PLL OFF tA Aperture delay 2.1 ns Aperture jitter 1.0 ps t1 Data setup time 8 10 ns t2 Data hold time 14 19 ns tD Data latency 6 Clocks tDR, tDF Data rise/fall time 0.5 2 3.5 ns Data valid (DV) duty cycle 30 45 55 % tDV Input clock rising to DV fall edge 16 19 21 ns 20MSPS With PLL ON tA Aperture delay 2.1 ns Aperture jitter 1.0 ps t1 Data setup time 10 12 ns t2 Data hold time 20 25 ns tD Data latency 6 Clocks tDR, tDF Data rise/fall time 0.5 2 3.5 ns Data valid (DV) duty cycle 30 45 55 % tDV Input clock rising to DV fall edge 20 25 30 ns 20MSPS With PLL OFF tA Aperture delay 2.1 ns Aperture jitter 1.0 ps t1 Data setup time 10 12 ns t2 Data hold time 20 25 ns tD Data latency 6 Clocks tDR, tDF Data rise/fall time 0.5 2 3.5 ns Data valid (DV) duty cycle 30 45 55 % tDV Input clock rising to DV fall edge 20 25 30 ns 8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS5237 |
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