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X25097VG-1.8 Datasheet(PDF) 3 Page - IC MICROSYSTEMS |
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X25097VG-1.8 Datasheet(HTML) 3 Page - IC MICROSYSTEMS |
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3 / 15 page  X25097 3 IDLock Memory Xicor’s IDLock Memory provides a flexible mechanism to store and lock system ID and parametric information. There are seven distinct IDLock Memory areas within the array which vary in size from one page to as much as half of the entire array. These areas and associated address ranges are IDLocked by writing the appropriate two byte IDLock instruction to the device as described in Table 1 and Figure 7. Once an IDLock instruction has been com- pleted, that IDLock setup is held in a nonvolatile Status Register (Figure 1) until the next IDLock instruction is issued. The sections of the memory array that are IDLocked can be read but not written until IDLock Protec- tion is removed or changed. Figure 1. Status Register/IDLock Byte Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the E2PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25097, followed by the 16-bit address, of which the last 10 bits are used (bits [15:10] specified to be zeroes). After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (03FFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the Read Operation Sequence illustrated in Figure 2. Read Status Operation If there is not a nonvolatile write in progress, the Read Status instruction returns the ID Lock byte from the Sta- tus Register which contains the ID Lock bits IDL2-IDL0 (Figure 1). The ID Lock bits define the ID Lock condition (Figure 1/Table1). The other bits are reserved and will return ’0’ when read. See Figure 3. If a nonvolatile write is in progress, the Read Status Instruction returns a HIGH on SO. When the nonvolatile write cycle is completed, the status register data is read out. Clocking SCK is valid during a nonvolatile write in progress, but is not necessary. If the SCK line is clocked, the pointer to the status register is also clocked, even though the SO pin shows the status of the nonvolatile write operation (See Figure 3). Write Sequence Prior to any attempt to write data into the X25097, the “Write Enable” latch must first be set by issuing the WREN instruction (See Table 1 and Figure 4). CS is first taken LOW. Then the WREN instruction is clocked into the X25097. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E2PROM memory array, the user then issues the WRITE instruction, followed by the 16 bit address and the data to be written. Only the last 10 bits of the address are used and bits [15:10] are specified to be zeroes. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 16 bytes of data to the X25097. The only restriction is the 16 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been previously written. For a byte or page write operation to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed. Refer to Figures 5 and 6 for detailed illustration of the write sequences and time frames in which CS going HIGH are valid. 7 6 5 4 3 2 1 0 0 0 0 0 0 IDL2 IDL1 IDL0 Note: Bits [7:3] specified to be “0’s” 7038 FRM T02.1 |
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