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X24645S8IG Datasheet(PDF) 1 Page - IC MICROSYSTEMS |
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X24645S8IG Datasheet(HTML) 1 Page - IC MICROSYSTEMS |
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1 / 18 page  Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection 64K 8192 x 8 Bit This X24645 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. © Xicor, 1995, 1996 Patents Pending Characteristics subject to change without notice 2783-3.5 5/13/96 T1/C0/D0 NS 1 X24645 FUNCTIONAL DIAGRAM FEATURES •2.7V to 5.5V Power Supply •Low Power CMOS —Active Read Current Less Than 1mA —Active Write Current Less Than 3mA —Standby Current Less Than 1∝A •Internally Organized 8192 x 8 •New Programmable Block Lock Protection —Software Write Protection —Programmable hardware Write Protect •Block Lock (0, 1/4, 1/2, or all of the E 2 PROM array) •2 Wire Serial Interface •Bidirectional Data Transfer Protocol •32 Byte Page Write Mode —Minimizes Total Write Time Per Byte •Self Timed Write Cycle —Typical Write Cycle Time of 5ms •High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years •Available Packages —8-Lead PDIP —8-Lead SOIC (JEDEC) —14-Lead SOIC (JEDEC) —20-Lead TSSOP DESCRIPTION The X24645 is a CMOS 65,536-bit serial E 2 PROM, internally organized 8192 x 8. The X24645 features a serial interface and software protocol allowing operation on a simple two wire bus. Two device select inputs (S1, S2) allow up to four devices to share a common two wire bus. A Write Protect Register at the highest address location, 1FFFh, provides three new write protection features: Software Write Protect, Block Write Protect, and Hardware Write Protect. The Software Write Protect feature prevents any nonvolatile writes to the X24645 until the WEL bit in the write protect register is set. The Block Write Protection feature allows the user to individually write protect four blocks of the array by programming two bits in the write protect register. The Programmable Hardware Write Protect feature allows the user to install the X24645 with WP tied to VCC, program the entire memory array in place, and then enable the hardware write protection by programming a WPEN bit in the write protect register. After this, selected blocks of the array, including the write protect register itself, are permanently write protected, as long as WP remains HIGH. START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR H.V. GENERATION TIMING & CONTROL WORD ADDRESS COUNTER XDEC YDEC D OUT ACK E 2 PROM 256 X 256 DATA REGISTER START CYCLE V CC R/W PIN V SS SDA SCL S 2 S 1 D OUT LOAD INC CK 8 2783 ILL F01 WRITE PROTECT REGISTER AND LOGIC WP ICmic IC MICROSYSTEMS TM |
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