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X24C01SG-3.5 Datasheet(PDF) 3 Page - IC MICROSYSTEMS |
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X24C01SG-3.5 Datasheet(HTML) 3 Page - IC MICROSYSTEMS |
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3 / 14 page  X24C01 3 DEVICE OPERATION The X24C01 supports a bidirectional bus oriented pro- tocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. There- fore, the X24C01 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are re- served for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C01 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Figure 1. Data Validity SCL SDA DATA STABLE DATA CHANGE 3837 FHD F06 |
Similar Part No. - X24C01SG-3.5 |
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Similar Description - X24C01SG-3.5 |
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