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MSP430F2101IDGV Datasheet(PDF) 3 Page - Texas Instruments |
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MSP430F2101IDGV Datasheet(HTML) 3 Page - Texas Instruments |
3 / 52 page MSP430x21x1 MIXED SIGNAL MICROCONTROLLER SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL NAME DW, PW, or DGV RGE I/O DESCRIPTION NAME NO. NO. I/O DESCRIPTION P1.0/TACLK 13 13 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input P1.1/TA0 14 14 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 15 15 I/O General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 16 16 I/O General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK/TCK 17 17 I/O General-purpose digital I/O pin / SMCLK signal output Test Clock input for device programming and test P1.5/TA0/TMS 18 18 I/O General-purpose digital I/O pin / Timer_A, compare: Out0 output Test Mode Select input for device programming and test P1.6/TA1/TDI/TCLK 19 20 I/O General-purpose digital I/O pin / Timer_A, compare: Out1 output Test Data Input or Test Clock Input for programming and test P1.7/TA2/TDO/TDI† 20 21 I/O General-purpose digital I/O pin / Timer_A, compare: Out2 output Test Data Output or Test Data Input for programming and test P2.0/ACLK/CA2 8 6 I/O General-purpose digital I/O pin / ACLK output Comparator_A+, CA2 input P2.1/INCLK/CA3 9 7 I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLK Comparator_A+, CA3 input P2.2/CAOUT/ TA0/CA4 10 8 I/O General-purpose digital I/O pin Timer_A, capture: CCI0B input/BSL receive Comparator_A+, output / CA4 input P2.3/CA0/TA1 11 10 I/O General-purpose digital I/O pin / Timer_A, compare: Out1 output Comparator_A+, CA0 input P2.4/CA1/TA2 12 11 I/O General-purpose digital I/O pin / Timer_A, compare: Out2 output Comparator_A+, CA1 input P2.5/CA5 3 24 I/O General-purpose digital I/O pin Comparator_A+, CA5 input XIN/P2.6/CA6 6 4 I/O Input terminal of crystal oscillator General-purpose digital I/O pin Comparator_A+, CA6 input XOUT/P2.7/CA7 5 3 I/O Output terminal of crystal oscillator general-purpose digital I/O pin Comparator_A+, CA7 input RST/NMI 7 5 I Reset or nonmaskable interrupt input TEST 1 22 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. VCC 2 23 Supply voltage VSS 4 2 Ground reference QFN Pad NA Package Pad NA QFN package pad connection to VSS recommended. † TDO or TDI is selected via JTAG instruction. NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. |
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