XC25BS7 datasheet(5/13 Pages) TOREX

Part #	XC25BS7

Description	PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits

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Manufacturer	TOREX [Torex Semiconductor]

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XC25BS7

Series

PARAMETER

SYMBOL

CONDITIONS

MIN.

MAX.

UNIT

Supply Voltage

VDD

3.3V (TYP.) operation

2.97

3.63

V

Input Frequency

fCLKin

(*1)

45.000

60.000

kＨｚ

Multiplier/Divider Ratio

N/M

Typical value is shown

(*1)

256

-

Output Frequency

fQ0

(*1)

11.520

15.360

MHz

Capacity Overload

(*3)

CL

-

15

pF

Output Start Time

(*2)(*3)

TON

fCLKin＝45kHz

0.05

20

ms

PARAMETER

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CIRCUIT

H Level Input Voltage

VIH

2.70

-

V

①

L Level Input Voltage

VIL

-

0.60

V

①

H Level Input Current

IiH

VCLKin=VDD-0.3V

-

3.0

μ

A

②

L Level Input Current

IiL

VCLKin=0.3V

-3.0

-

μ

A

②

H Level Output Voltage

VOH

VDD=2.97V, IOH=-4mA

2.50

-

V

③

L Level Output Voltage

VOL

VDD=2.97V, IOL= 4mA

-

0.40

V

③

Supply Current 1

IDD1

VDD=3.63V, CE= 3.63V

-

3.0

6.0

mA

④

Supply Current 2

IDD2

VDD=3.63V, CE= 0.0V

-

10

μ

A

④

CE H Level Voltage

VCEH

2.70

-

V

①

CE L Level Voltage

VCEL

-

0.45

V

①

CE Pull-Down Resistance 1

Rdn1

CE=VDD

0.2

1.0

1.8

MΩ

⑤

CE Pull-Down Resistance 2

Rdn2

CE=0.1 x VDD

10

30

60

kΩ

⑤

Output Off Leak Current

IOZ

VDD=Q0=3.63V, CE= 0.0V

-

10

μ

A

⑥

PARAMETER

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CIRCUIT

Output Rise Time

(*1)

Tr

(20% ~ 80%)

-

2.5

5.0

ns

①

Output Fall Time

(*1)

Tf

(20% ~ 80%)

-

2.5

5.0

ns

①

fQ0≦60MＨｚ

45

50

55

％

Output Signal Duty

(*1)

Duty

fQ0≧60MＨｚ

40

50

60

％

①

PLL Output Signal Jitter 1

(*1)

TJ1

1σ (Output Period)

-

20

-

ps

①

PLL Output Signal Jitter 2

(*1)

TJ

２

Peak to Peak (Output Tracking)

-

20

-

ns

①

■ELECTRICAL CHARACTERISTICS (Continued)

●Recommended Operating Conditions: XC25BS7001xx (256 multiplication, Input 48kHz (TYP.)) 3.3V (TYP.)

Tested below Ta=25

OC

NOTE:

*1: Connected CIN=0.1μF of a ceramic capacitor between the VDD pin the VSS pin while testing.

*2: Time until signal via the Q0 pin flows stably from applying supply voltage to the VDD pin and control voltage to the CE pin while

applying the input signal to the CLKin pin.

*3: The value indicated at output start time is designed values which are not guaranteed values.

●DC Characteristics: XC25BS7001xx (256 multiplication, Input 48kHz (TYP.) ) 3.3V (TYP.)

Test Conditions: VDD=3.3V, fCLKin=48kHz, Multiplier ratio=256, Ta=25℃, No Load

●AC Characteristics: XC25BS7001xx (256 multiplication, Input 48kHz (TYP.)) 3.3V (TYP.)

Test Conditions: VDD=3.3V, fCLKin=48kHz, Multiplier ratio=256, Ta=25℃, CL=15pF

NOTE:

*1: Values indicated at the AC Characteristics are designing values, which are not guaranteed values.

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