eorex
EM48AM1684VTC
Jul. 2006
www.eorex.com
AC Operating Test Characteristics (Continued)
(VDD=3.3V±0.3V, TA=0°C ~70°C for extended grade)
-7
-7.5
Symbol
Parameter
Min.
Max..
Min.
Max.
Units
tRC
ACTIVE to ACTIVE Command
Period
(Note 6)
62
67
ns
tRAS
ACTIVE to PRECHARGE
Command Period
(Note 6)
42
100K
45
100K
ns
tRP
PRECHARGE to ACTIVE
Command Period
(Note 6)
20
20
ns
tRCD
ACTIVE to READ/WRITE Delay
Time
(Note 6)
20
20
ns
tRRD
ACTIVE(one) to ACTIVE(another)
Command
(Note 6)
14
15
ns
tCCD
READ/WRITE Command to
READ/WRITE Command
1
1
CLK
tDPL
Date-in to PRECHARGE
Command
2
2
CLK
tBDL
Date-in to BURST Stop Command
1
1
CLK
CL=3
3
3
tROH
Data-out
to High
Impedance from
PRECHARGE Command
CL=2
2
2
CLK
tREF
Refresh Time (8,192 cycle)
64
64
ms
* All voltages referenced to VSS.
Note 6: These parameters account for the number of clock cycles and depend on the operating frequency
of the clock, as follows:
The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole
number)
Recommended Power On and Initialization
The following power on and initialization sequence guarantees the device is preconditioned to each user’s
specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on
voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. (CLK signal started at same
time)
After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the
precharge command.
To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be
held high during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR)
are also required, and these may be done before or after programming the Mode Register.
8/17
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