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TS824CX5GRF Datasheet(PDF) 2 Page - Taiwan Semiconductor Company, Ltd |
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TS824CX5GRF Datasheet(HTML) 2 Page - Taiwan Semiconductor Company, Ltd |
2 / 8 page TS823/824/825 Series Microprocessor Supervisory Circuit with Watchdog Timer & Manual Reset 2/8 Version: B07 Electrical Specifications (Ta = 25oC, unless otherwise noted) Parameter Conditions Symbol Min Typ Max Unit Input Supply Voltage Vdd 1.0 -- 5.5 V Supply Current WDI and MRB unconnected Idd -- 3 10 uA TS823/824/825CX5A 4.56 4.63 4.7 TS823/824/825CX5B 4.31 4.38 4.45 TS823/824/825CX5D 3.03 3.08 3.13 TS823/824/825CX5E 2.89 2.93 2.97 TS823/824/825CX5F 2.59 2.63 2.67 TS823/824/825CX5G 2.28 2.32 2.36 Reset Threshold TS823/824/825CX5H VTH 2.15 2.19 2.23 V RESET Output Voltage Low Vdd<VTH(MIN), ISINK =1.2mA, VOL -- -- 0.5 V (RESET) Output Voltage High Vdd>VTH(MAX), ISOURCE=0.5mA VOH 0.8 Vdd -- -- V Vdd to Reset Delay Vdd =VTH - 100mV TD1 -- 40 -- uS Reset Active Timeout Period Ta=-40 oC ~+85oC TD2 140 210 280 mS Watchdog Timeout Period TWD 1120 1760 2400 mS WDI Pulse Width TWDI 50 -- -- nS WDIIL -- -- 0.7 V WDI Input Threshold Vdd = VTH x 1.2 WDIIH 0.8 Vdd -- -- V WDI =0V IIL -15 -8 0.7 uA WDI Input Current WDI =Vdd = 5V IIH -- 8 15 uA MRIL -- -- 0.7 V MR Input Threshold Vdd=VTH x 1.2 MRIH 0.8 Vdd -- -- V MR Pulse Width TWMR 1 -- -- uS MR Noise Immunity Pulse width with no reset -- 100 -- nS MR to Reset Delay Vdd = VTH - 100mV TDMR -- 500 -- nS MR Pull Up Resistance 80 -- 120 KΩ Input Supply Voltage Ta=-40 oC~+85oC VCC 1.0 -- 5.5 V Detail Description Pin Function Pin Name Pin Description Reset Active Low GND Ground (Reset) Active High MR This pin is active low. Pulling this pin low to forces a reset. After a low to high transition reset remains asserted for exactly one reset timeout period. This pin is internally pulled high. If this function is unused then float this pin or tie it to Vdd. WDI Watch Dog Input. Any transition on this pin will reset the Watch Dog timer. If this pin remains high or low for longer than the Watch Dog interval then a reset is asserted. Float or tri-state this pin to disable the Watch Dog feature. Vdd Positive power supply. A reset is asserted after this voltage drops below a predetermined level. After Vdd rises above that level reset remains asserted until the end of the reset timeout period. |
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