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MPC8360ETVVAJFGA Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MPC8360ETVVAJFGA Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 112 page  MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 2 Freescale Semiconductor Overview 1Overview This section describes a high-level overview including features and general operation of the MPC8360E/58E PowerQUICC™ II Pro processor. A major component of this device is the e300 core which includes 32 Kbytes of instruction and data cache and is fully compatible with the PowerPC™ 603e instruction set. The new QUICC Engine™ module provides termination, interworking, and switching between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine module's enhanced interworking eases the transition and reduces investment costs from ATM to IP based systems. The other major features include a dual DDR SDRAM memory controller for the MPC8360E, which allows equipment providers to partition system parameters and data in an extremely efficient way, such as using one 32-bit DDR memory controller for control plane processing and the other for data plane processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine. Figure 1. MPC8360E Block Diagram Memory Controllers GPCM/UPM/SDRAM 32/64 DDR Interface Unit PCI Bridge Local Bus Bus Arbitration DUART Dual I2C 4 Channel DMA Interrupt Controller Protection & Configuration System Reset Clock Synthesizer System Interface Unit (SIU) Local Baud Rate Generators Multi-User RAM Parallel I/O Accelerators Dual 32-bit RISC CP Serial DMA & 2 Virtual DMAs 2 GMII/ RGMII/TBI/RTBI 8 MII/ RMII 8 TDM Ports 2 UTOPIA/POS (124 MPHY) Serial Interface QUICC Engine Module JTAG/COP Power Management Timers FPU Classic G2 MMUs 32KB D-Cache 32KB I-Cache Security Engine e300 Core PCI DDRC1 Time Slot Assigner DDRC2 |
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Similar Description - MPC8360ETVVAJFGA |
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