UPC1251GR-9LG datasheet(4/12 Pages) NEC

Part #	UPC1251GR-9LG

Description	BIPOLAR ANALOG INTEGRATED CIRCUIT SINGLE POWER SUPPLY DUAL OPERATIONAL AMPLIFIERS

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Manufacturer	NEC [NEC]

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Data Sheet G17929EJ3V0DS

4

μPC1251GR-9LG, μPC1251MP-KAA, μPC358GR-9LG

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

MIN.

TYP.

MAX.

Unit

Power Supply Voltage (Split)

V±

±1.5

±15

V

Power Supply Voltage (V− = GND)

V+

+3

+30

V

ELECTRICAL CHARACTERISTICS

μPC1251GR-9LG, μPC1251MP-KAA, μPC358GR-9LG (TA = 25°C, V+ = +5 V, V− = GND)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input Offset Voltage

VIO

RS = 0

Ω

±2

±7

mV

Input Offset Current

IIO

±5

±50

nA

Input Bias Current

Note1

IB

14

250

nA

Large Signal Voltage Gain

AV

RL

≥ 2 kΩ

25000

100000

Circuit Current

Note2

ICC

RL =

∞, IO = 0 A

0.7

1.2

mA

Common Mode Rejection Ratio

CMR

65

70

dB

Supply Voltage Rejection Ratio

SVR

65

100

dB

Output Voltage Swing

VO

RL = 2 k

Ω (Connect to GND)

0

V+

− 1.5

V

Common Mode lnput Voltage Range

VICM

0

V+

− 1.5

V

Output Source Current

IO SOURCE VIN (+) =

+1 V, VIN (−) = 0 V

20

40

mA

Output Sink Current

IO SINK1

VIN (−) =

+1 V, VIN (+) = 0 V

10

20

mA

IO SINK2

VIN (−) =

+1 V, VIN (+) = 0 V, VO = 200 mV

12

50

μA

Channel Separation

f = 1 to 20 kHz

120

dB

μPC1251GR(5)-9LG, μPC1251MP(5)-KAA, μPC358GR(5)-9LG (TA = 25°C, V+ = +5 V, V− = GND)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input Offset Voltage

VIO

RS = 0

Ω

±2

±3

mV

Input Offset Current

IIO

±5

±50

nA

Input Bias Current

Note1

IB

14

60

nA

Large Signal Voltage Gain

AV

RL

≥ 2 kΩ

50000

100000

Circuit Current

Note2

ICC

RL =

∞, IO = 0 A

0.7

0.9

mA

Common Mode Rejection Ratio

CMR

65

70

dB

Supply Voltage Rejection Ratio

SVR

65

100

dB

Output Voltage Swing

VO

RL = 2 k

Ω (Connect to GND)

0

V+

− 1.5

V

Common Mode lnput Voltage Range

VICM

0

V+

− 1.4

V

Output Source Current

IO SOURCE VIN (+) =

+1 V, VIN (−) = 0 V

30

40

mA

Output Sink Current

IO SINK1

VIN (−) =

+1 V, VIN (+) = 0 V

15

20

mA

IO SINK2

VIN (−) =

+1 V, VIN (+) = 0 V, VO = 200 mV

30

50

70

μA

Channel Separation

f = 1 to 20 kHz

120

dB

Notes1. The input bias current flows in the direction where the IC flows out because the first stage is configured with a

PNP transistor.

2. This is a current that flows in the internal circuit. This current will flow irrespective of the channel used.

<R>

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