Detailed Description

The MAX3674 is a high-performance wide-frequency

range clock synthesizer. It integrates a crystal oscillator,

PLL, programmable dividers, configuration registers,

two differential PECL outputs buffers (QA, QB), and an

LVCMOS lock indicator output (Figure 1). Using a low-

frequency clock as a reference, the internal PLL gener-

ates a high-frequency output clock with excellent jitter

performance. The programmable dividers make it possi-

ble to generate a wide range of output frequencies

(21.25MHz to 1360MHz) and perform frequency margin-

ing using the increment and decrement functions.

Reference Clock

An integrated oscillator provides the low-frequency ref-

erence clock for the PLL. This oscillator requires an

external quartz crystal connected between XTAL1 and

XTAL2 (Table 12). Alternatively, an LVCMOS-compati-

ble clock source can be connected to the REF_CLK

input to serve as the reference clock.

Phase-Locked Loop (PLL)

The reference clock passes through a predivider (P)

before entering the PLL. The PLL contains a phase-fre-

quency detector (PFD), lowpass filter, and voltage-con-

trolled oscillator (VCO) with a 1360MHz to 2720MHz

operating range. The VCO output is connected to the

PFD input through a feedback divider (M). The PFD

control signal that keeps the VCO locked to the refer-

ence clock. After scaling the VCO output with postdi-

PECL output buffers. To minimize noise-induced jitter,

the core logic and output buffers.

Configuration Registers and Dividers

Output frequency depends on the reference clock fre-

through configuration logic that uses either a serial or

parallel interface as selected by the PLOAD input. The

parallel interface uses the values at the P, M[9:0],

NA[2:0], and NB parallel inputs to configure the internal

vides read and write access to configuration registers.

LVPECL Outputs

The high-frequency outputs, QA and QB, use differen-

tial PECL buffers designed to drive a pair of transmis-

sion lines terminated 50

differential outputs can be enabled/disabled indepen-

dently using the CLK_STOPx inputs. The CLK_STOPx

inputs are synchronized to the output clock signal to

eliminate the possibility of producing runt pulses. Using

the postdivider NB, the secondary output QB can be

configured to run at 1x or 1/2x the frequency of the pri-

mary output QA.

High-Performance, Dual-Output, Network Clock

Synthesizer

_______________________________________________________________________________________

9

XTAL

XTAL1

REF_SEL

XTAL2

REF_CLK

QA

QB

LOCK

/ P

(2, 4)

/ NB

(1, 2)

PLL

1360MHz TO

2720MHz

PLL

CONFIGURATION

REGISTERS

/ NA

(2, 4, 8, 16,

32, 64)

/ M

SDA

SCL

ADR[1:0]

P

PLOAD

M[9:0]

NA[2:0]

NB

CLK_STOPx

BYPASS

MR

MAX3674

Figure 1. Functional Diagram