TD7624AFN

2001-03-01 9/21

l 18-bit DATA TRANSMISSION :

During a high level of the enable signal, the data is clocked into the register on the falling edge of the

clock.

The clock number during a high level of the enable signal must be set to 18-bit for the latch condition.

(The number of clock rising edges is 18).

For latch timing, the first four bits, which control the bandswitch buffers, are loaded at the fifth rising

edge of the clock, and the data is updated.

The programmed counter data transmits the 18-bit data, latched on the falling edge of the enable signal.

During 18-bit data transmission, “N14” programmable counter data is constantly set to [0] , and the

phase comparator reference frequency divider ratio is automatically set to “1 / 64”.

Details of the data timing, see the data timing chart (Figure 1)

l 19-bit DATA TRANSMISSION :

During a high level of the enable signal, the data is clocked into the register on the falling edge of the

clock.

The clock number during a high level of the enable signal must be set to 19-bit for the latch condition.

(The number of clock rising edge is 19).

For latch timing, the first four bits, which control the bandswitch buffers, are loaded at the fifth rising

edge of the clock, and the data is updated.

The programmed counter data transmits the 19-bit data, latched on the falling edge of the enable signal.

During 19-bit data transmission, the phase comparator reference frequency divider ratio is automatically

set to “1 / 80” or “1 / 128” in BUS-SW mode.

Details of the data timing, see the data timing chart (Figure 1)