TD7623AFN

2001-03-01 10/19

― I

READ mode, which status data.

WRITE and READ mode are set using the last bit (R / W bit) of the address byte.

If the last address bit is set to [0], WRITE mode is set ; if set to [1] READ mode is set.

Address can be set using the hardware bits. Three programmable address can be programmed.

The address for the hardware bit setting can be selected by applying voltage to the address setting pin

(ADR : Pin 15). An address is selected according to the set bits.

When the correct address byte is received, during acknowledgment, serial data (SDA) line is “Low”.

If WRITE mode is set at this time, when the data byte is programmed, the serial data (SDA) line is “Low”

during the next acknowledgment.

When WRITE mode is set, Byte 1 segment the address data ; Bytes 2 and 3 segment the frequency data ;

Byte 4 segment the divider ratio setting and function setting data ; and Byte 5 segment the output port

data.

Data are latched and transferred at the end of Byte 3, Byte 4 and Byte 5.

Byte 2 and Byte 3 are latched and transferred is done with a two byte set (Byte 2+Byte 3).

Once a correct address is received and acknowledged, the data type is determined according to [0] or

[1]set in the first bit of the next byte. That is, if the first bit is [0], the data are frequency data ; if [1],

function setting or output port data.

the address again. (Ex : Frequency sweep is possible with additional frequency data.)

If data transmission is aborted, data programmed before the abort are valid.

Byte 1 can set the hardware bit with address data.

The hardware bit is set with voltage applied to the address setting pin (ADR : Pin 15).

Bytes 2 and 3 are stored in the 15-bit shift register with counter data for the frequency setting, and

control the 15-bit programmable counter ratio.

The program frequency can be calculated in the following formula :

fosc :

Program frequency

:

Phase comparator reference frequency (Step frequency)

N

:

Counter total ratio

The reference frequency divider ratio can be set to 1 / 12, 1 / 16, 1 / 64 and 1 / 80.

The step frequency are 333.33 kHz, 250 kHz, 62.5 kHz and 50 kHz.

Byte 4 is a control byte used to set function. Bit 2 (CP) controls the output current of the charge-pump

circuit. When bit 2 is set to [0] : the output current is set to ±200 µA ; when set to [1] , ±800 µA.

reference signal output, and counter divider output.

For details of test mode, see the test mode setting table.

Bit 6 (RSa) and Bit 7 (RSb) are used to set the X’tal reference frequency divider ratio.

For details of the X’tal reference frequency divider ratios, see the table for X’tal reference frequency

divider ratios.

Bit 8 (OS) is used to set the charge-pump drive amplifier output setting. When bit 8 is set to [0] the

output is ON (Normal Use) ; when set to [1] the output is OFF (Tr. Output is Low Level).

Byte 5 is used to set and control the output port (Bands 1~4).

When an output port set to [0] is OFF ; when set to [1] is ON.

Two output ports can be operation turned on, but be sure to keep the total output current under 40 mA.