HM6268P-35 datasheet(7/9 Pages) ETC2

Part #	HM6268P-35

Description	4096-word X 4-bit High-Speed CMOS Static RAM

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Write Timing Waveform (1) (

WE Controlled)

7

HM6268 Series

A write cycle occurs during the overlap of a low

CS and a low WE (tWP).

tWR is measured from the earlier of CS or WE going high to the end of the write cycle.

During this period, I/O pins are in the output state so input signals of opposite

phase to the outputs must not be applied.

If

CS is low during this period, I/O pins are in the output state, so data input signals

of opposite phase to the outputs must not be applied.

Dout has the same phase as write data in this write cycle, if tWR is long enough.

Notes: 1.

2.

3.

4.

5.

tWC

tCW

tAW

tWP

*1

tAS

tWR *

2

tDW

tWZ

High impedance

*5

*4

tOH

tOW

*3

Address

CS

WE

Dout

Din

Valid Data

tDH

*4

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HM6268P-35 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers

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