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t

(LOW)

t

f

t

r

t

(HD:STA)

t

(SU:DAT)

t

(HIGH)

t

(HD:DAT)

t

(HD:STA)

t

(BUF)

SCLK

SDATA

t

(SU:STO)

P

S

S

P

SCLK

SDATA

Start

Stop

t

(LOW:SEXT)

t

(LOW:MEXT)

t

(LOW:MEXT)

t

(LOW:MEXT)

SCLK

ACK

(1)

SCLK

ACK

(1)

t

(SU:STA)

bq20z75

SLUS723 – JULY 2007

SMBus Timing Characteristics (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Error signal/detect (see Figure 1)

25

35

µs

Clock low period (see Figure 1)

4.7

µs

Clock high period (see Figure 1)

4.0

50

µs

Cumulative clock low slave extend time

25

µs

10

µs

Figure 1)

Clock/data fall time

300

ns

Clock/data rise time

1000

ns

(1)

(2)

progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).

(3)

(4)

(5)

(6)

A.

SCLKACK is the acknowledge-related clock pulse generated by the master.

Figure 1. SMBus Timing Diagram

10

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