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M4T32-BR12SH6 Datasheet(PDF) 11 Page - STMicroelectronics |
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M4T32-BR12SH6 Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 28 page M48T35AV Operation modes 11/28 Table 4. Write mode AC characteristics 2.3 Data retention mode With valid VCC applied, the M48T35AV operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window (see Figure 13, Table 10, and Table 11 on page 21). All outputs become high impedance, and all inputs are treated as “don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T35AV may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T35AV for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles prior to processor stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max). Symbol Parameter(1) 1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted). M48T35AV Unit Min Max tAVAV WRITE cycle time 100 ns tAVWL Address valid to WRITE enable low 0 ns tAVEL Address valid to chip enable low 0 ns tWLWH WRITE enable pulse width 80 ns tELEH Chip enable low to chip enable high 80 ns tWHAX WRITE enable high to address transition 10 ns tEHAX Chip enable high to address transition 10 ns tDVWH Input valid to WRITE enable high 50 ns tDVEH Input valid to chip enable high 50 ns tWHDX WRITE enable high to input transition 5 ns tEHDX Chip enable high to input transition 5 ns tWLQZ (2)(3) 2. CL = 5pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. WRITE enable low to output Hi-Z 50 ns tAVWH Address valid to WRITE enable high 80 ns tAVEH Address valid to chip enable high 80 ns tWHQX (2)(3) WRITE enable high to output transition 10 ns |
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Similar Description - M4T32-BR12SH6 |
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