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TB62702P Datasheet(PDF) 4 Page - Toshiba Semiconductor |
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TB62702P Datasheet(HTML) 4 Page - Toshiba Semiconductor |
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4 / 11 page  TB62702P/F 2006-06-14 4 SWITCHING CHARACTERISTICS (Ta = 25°C, VDD = 5 V, VOUT = 30 V, RL = 1150 Ω, CL = 15 pF, "H" = VIH, "L" = VIL) CHARACTERISTIC SYMBOL TEST CONDITION MIN TYP. MAX UNIT CLK− OUTn LAT = "H", CLR = "H", EN = "H" ― ― 250 CLK− OUTn LAT = "H", EN = "H" ― ― 250 LAT − OUTn CLR = "H", EN = "H" ― ― 200 Propagation Delay Time (Low−to−High) EN− OUTn tpLH LAT = "H", CLR = ”H” ― ― 150 ns CLK− OUTn LAT = "H", CLR = "H", EN = "H" ― ― 250 LAT − OUTn CLR = "H", EN = "H" ― ― 200 Propagation Delay Time (High−to−Low) EN− OUTn tpHL LAT = "H", CLR = "H" ― ― 150 ns CLK− LAT tsetup (L) ― ― ― 50 Set Up Time CLK−S−IN tsetup (D) ― ― ― 35 CLK− LAT thold (L) ― ― ― 105 Hold Time CLK−S−IN thold (D) ― ― ― 50 ns Clock Pulse Width tw CLK ― ― ― 100 Latch Pulse Width tw LAT ― ― ― 50 Clear Pulse Width tw CLR ― ― ― 50 Enable Pulse Width tw EN ― ― ― 400 ns tor OUTn ― ― 1000 Output Rise Time tr S−OUT, VSS = 0V ― ― 50 tof OUTn ― ― 150 Output Fall Time tf S−OUT, VSS = 0V ― ― 50 ns fMAX1 Duty = 50% Cascade connected 5 8 ― Maximum Clock Frequency fMAX2 Duty = 50% 6 12 ― MHz RECOMMENDED TIMING CONDITIONS (Ta = −40~85°C, VDD = 4.5~5.5 V, VSS = 0) CHARACTERISTIC SYMBOL TEST CONDITION MIN TYP. MAX UNIT Clock Pulse Width tw CLK ― 100 ― ― ns Enable Pulse Width tw EN ― 400 ― ― µs Latch Pulse Width tw LAT ― 100 ― ― ns Clear Pulse Width tw CLR ― 100 ― ― ns Data Set Up Time tsetup ― 100 ― ― ns Data Hold Time thold ― 150 ― ― ns |
Similar Part No. - TB62702P_06 |
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Similar Description - TB62702P_06 |
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