P10C68/P11C68

9

STORE CYCLE 2 : E (BAR) CONTROLLED

(See note 13)

Standard

Alternative

Parameter

Store cycle time

NE (bar) set-up to chip enable

Write enable wet-up to chip enable

Chip enable to NE (bar) rise

Output disable set-up to E (bar) fall

Symbol

Notes

17

18

Units

ms

ns

ns

ns

ns

Min.

0

0

45

0

Max.

10

Min.

0

0

45

0

P10C68-35

P10C68-45

Max.

10

NOTES

16. E (bar), G (bar), NE (bar) and W (bar) must make the transition between VIH(max) to VIL(max), or VIL(max) to VIH(min) in a

monotonic fashion.

17. Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Note that store cycles are inhibited/aborted

by Vcc <3.3V (STORE inhibit).

18. Once twc has been satisfied by NE (bar), G (bar), W (bar) and E (bar) the store cycle is completed automatically, ignoring all

inputs. Any of NE (bar), G (bar), W (bar) or E (bar) may be used to terminate the store initiation cycle.

NE

G

W

E

DQ

(DATA

OUT)

HIGH IMPEDANCE

Figure 9. STORE CYCLE 1: W (bar) controlled timing diagram (see note 16).

NE

W

E

DQ

(DATA

OUT)

HIGH IMPEDANCE

G

Figure 10. STORE CYCLE 2: E (bar) controlled timing diagram (see note 16).