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TB7004FL Datasheet(PDF) 3 Page - Toshiba Semiconductor |
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TB7004FL Datasheet(HTML) 3 Page - Toshiba Semiconductor |
3 / 16 page TB7004FL 2007-11-13 3 Pin Configuration Pin Description Symbol Pin No. Description Notes CGND 1, 6, 51, Tab Signal ground for control circuitry Connect to PGND. NC 2 No-connect pin VGIN 3 Power supply for low-side MOSFET gate drive VCIN 4 Power supply for control circuitry BOOT 5 Bootstrap capacitor connection GH 7 High-side MOSFET gate signal For monitoring purposes VIN 8 to 20, Tab Input pins. Connected to an input of the on-chip the DC-DC converter. VSWH 21, 40 to 50, Tab Output pins. Output inductor connection PGND 22 to 39 Power ground GL 52 Low-side MOSFET gate signal For monitoring purposes THDN 53 Open-drain output that indicates that thermal shutdown (TSD) has been tripped. An external pull-up resistor should be added to the THDN pin. Held Low in thermal shutdown mode. REG5V 54 Internal 5-V regulator output DISBL# 55 Disable signal for internal circuitry. Setting DISBL# High enables internal circuitry. Setting DISBL# Low disables internal circuitry. Accepts both 5-V and 12-V signals. PWM 56 3-state enable input VIN (Bottom View) VSWH CGND PWM DISBL# REG5V THDN GL CGND VSWH VSWH VSWH VSWH VSWH VSWH VSWH VSWH VIN VIN VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND PGND PGND 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 |
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